In article <vggu8r83404u22[at]news.supernews.com>,
"Dan Johnson" <danieljohnson[at]vzavenue.net> wrote:

> > Why is that obvious?
> >
> > When you're doing research, you try to minimize the number of variables.
> > That's what Apple did.
>
> Apple was not doing research, they were doing marketing; they
> did *not* minimize the number of variables; they used different
> GCC builds, different malloc libraries, etc.

Here's a hint: They're different architectures. They had no choice.

--
Trev

"Hypotheses are initially assumed false, by definition. Science is about
proving them true." - Daniel Seriff

"Trevor Zion Bauknight" <trevzb[at]comcast.net> wrote in message
news:trevzb-697DB1.15335007072003[at]news.fu-berlin.de...
> In article <vggu8r83404u22[at]news.supernews.com>,
> "Dan Johnson" <danieljohnson[at]vzavenue.net> wrote:
> > Apple was not doing research, they were doing marketing; they
> > did *not* minimize the number of variables; they used different
> > GCC builds, different malloc libraries, etc.
>
> Here's a hint: They're different architectures. They had no choice.

That is of course true, but had they been trying to use
the most similar software they could, they could certainly
have come rather closer than they did.

I therefore conclude that they were not trying to do that.

http://www.arstechnica.com/cpu/03q2/ppc970-interview/ppc970-interview-2.html

At this point, Edelsohn is talking about the machine description file
(power4.md) that gcc uses to optimize for the Power4 and the 970. He's
the author of this file, and he and I had had an email conversation
about it previously because it appeared that the vector latencies
listed in it were wrong. As it turns out, they were in fact wrong
before WWDC, but the version of gcc that Apple was using for WWDC had
the correct values in it. (I'd imagine that this pre-WWDC obfuscation
of the 970's vector latencies was done deliberately, but I forgot to
ask him about that.)

One interesting fact that I learned about gcc is that the Power4 and
970's peculiar group dispatch scheme and issue queue structure doesn't
quite fit with gcc's internal model of what a processor should look
like. As a result, the L1 cache latency number (and I think some of
the other numbers, as well) in the machine description file had to be
altered from their true value in order to get the best performance out
of gcc.

David Edelsohn: ...and gcc is modeling this [i.e. the L1 cache
latency] with one more additional cycle because we've seen a
benefit... The gcc scheduler is not really designed ideally for a
processor like the 970 and the Power4 and others, and that's a lot of
what the IBM and Apple teams have worked on, due to the complexity of
the processor with the dispatch groups and the whole way it dispatches
and issues and what parts are in-order and what parts are
out-of-order, trying to better instruct the compiler how to arrange
code to match that. So there are certain places where we give it [i.e.
gcc] information that's more ideal for what it needs to generate than
for exactly describing the processor. So again that's a lot of what
IBM and Apple have been working on... that was one of the things that
we're continuing to work on to try to get the best performance out of
the processor.

......
......
Finally, not to return to the tiresome post-WWDC SPEC benchmark
debate, but the interview also brought home in a very fascinating way
the compiler's pivotal role in the whole hardware-software ecosystem.
Specifically, a design like the 970, which strays in some significant
ways from the standard processor model presumed by a cross-platform
compiler like gcc, isn't going to reach its full performance potential
without a more custom-fitted compiler. So it's good to know that Apple
and IBM are working together on this issue, and hopefully they'll have
made even further headway by the time the first G5 towers start to
move out into the market.

Arun Gupta wrote:
> So it's good to know that Apple and IBM are working together
> on this issue, and hopefully they'll have made even further headway
> by the time the first G5 towers start to move out into the market.

Do you know where IBM's 'xlc' compiler will fit in for Apple/IBM in the
future? I imagine that Apple needs the obj-c elements in gcc, but I wonder
where IBM is going (with their Linux-based PPC servers, etc).

(I'm assuming that xlc would be more closely matched to the Power
Architecture.)